Reconfigurable Computing Week

IEEE Computer Society - Italy chapter technically co-sponsored the Reconfigurable Computing Week, an initiative of the DRESD research group at Politecnico di Milano. The website, with all the materials, can be reached at http://www.dresd.org/rcw

Talks:

Reconfigurable computing: lock and load

The concept of reconfigurable computing has been around since the 1960s, when Gerald Estrin, a computer scientist at the University of California, Los Angeles, proposed the concept of a computer consisting of a standardprocessor augmented by array of reconfigurable hardware. In recent years, a lot of work has been done in the so called reconfigurable computing area and the evolution of reconfigurable devices has brought to significantly increase their size, capacity and performance. Reconfigurable systems, while providing new interesting features in the field of hardware/software co-design, and more in general in the embedded system design, also introduce new problems in their implementation and management. This is particularly true for systems that implement self partial reconfiguration.Therefore, the first set of talks will guide you through the basic definition and idea in the reconfigurable computing area, introducing a short historical overview of this field, presenting an overall and comprehensive state of the art of reconfigurable architecture, trying to motivate the reason behind the choice of FPGA as target-architecture. The concluding talk of the day will present the different scenarios (i.e. flexibility, resource lack…) where the reconfiguration can be effective showing also the drawbacks introduced by this new feature. We will show the presence of two different kinds of limits, theoretical and physical ones, trying to highlight possible solutions to both of these.

FPGA technologies description and design flows for SoPC

Nowadays, the most commonly used reconfigurable devices are FieldProgrammable Gate Arrays (FPGAs), employed both as a component of more complex systems (playing the role of a co-processor), and asSystem-on-Programmable-Chip (SoPC), integrating all system components. Within this context, especially interesting is the scenario of dynamically reconfigurable system, in which hardware reconfiguration is carried out without necessarily having to cease execution of those parts of the system that are not involved. The successful deployment of such complex and reconfigurable embedded systems to the market requires the identification, formalization, and implementation of concepts, methods, and tools that are able to ease the development of the software components and the implementation of the system architecture.

Reconfiguration technologies and DRESD contribution

The most recent enhancements of reconfigurable technologies envision the possibility to implement real-world systems capable of adapting their behavior and resources thousand times a second, according to the surrounding environment evolution. This capability would widen the horizons of embedded digital systems applications. These talks will discuss the possibility of implementing a reconfigurable architecture, highlighting pros and cons of different proposed solutions. There have been different proposals to build reconfigurable computing engines to obtain high performance at low cost by specializing the computing engine to the computation task. What seems to be neglected so far is the full exploitation of the ability to partially reconfigure the FPGA at runtime. In such a context the DRESD work will be presented showing how it can answer to some open issues, presenting the current state of its workwith also the future steps.